DescriptionQ172
Q172DesignAMDASIC interview problem
Implement a wrapping four-bit counter
TechniquesDesignRTL
DifficultyEasy
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A small status counter increments only when enabled and wraps naturally from 15 to 0. Write synthesizable SystemVerilog for the counter.
Starting declarationSystemVerilog
input logic clk
input logic reset
input logic enable
output logic [3:0] count
synchronous active-high resetExample input and output
Use this case to check your interpretationInput
Case 1: reset=1 at a rising edge
Case 2: count=4'h7 and enable=1
Case 3: count=4'hF and enable=1Output
Case 1: Gives count=0.
Case 2: Gives 4'h8 after the edge.
Case 3: Gives 4'h0 after the edge.Explanation
The shown result follows by applying this rule: Reset, increment, hold, and wrap behavior are all explicit. The cases also demonstrate this requirement: When enable is zero, hold count; no error or saturation flag is required.
02
Requirements (4)
- Use always_ff @(posedge clk) and nonblocking assignment.
- Give reset priority and set count to 4'h0 on a reset edge.
- When enable is one, assign count <= count + 4'd1 so four-bit overflow wraps.
- When enable is zero, hold count; no error or saturation flag is required.