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Hardware interview practice

Implement a wrapping four-bit counter

EasyRTL DesignSystemVerilog

A small status counter increments only when enabled and wraps naturally from 15 to 0. Write synthesizable SystemVerilog for the counter.

Starting point

Question code

input logic clk
input logic reset
input logic enable
output logic [3:0] count
synchronous active-high reset
Reviewed example

Work through one case

Input
Case 1: reset=1 at a rising edge
Case 2: count=4'h7 and enable=1
Case 3: count=4'hF and enable=1
Expected output
Case 1: Gives count=0.
Case 2: Gives 4'h8 after the edge.
Case 3: Gives 4'h0 after the edge.

The shown result follows by applying this rule: Reset, increment, hold, and wrap behavior are all explicit. The cases also demonstrate this requirement: When enable is zero, hold count; no error or saturation flag is required.

What to cover

Requirements

  1. Use always_ff @(posedge clk) and nonblocking assignment.
  2. Give reset priority and set count to 4'h0 on a reset edge.
  3. When enable is one, assign count <= count + 4'd1 so four-bit overflow wraps.
  4. When enable is zero, hold count; no error or saturation flag is required.