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DescriptionQ149
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Q149DVASIC interview problem

Clear-on-Read Status Bit Stays Set

TechniquesDVWaveform DebuggingRegisters
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

Each column is one rising clock edge. A read of status address 0x30 is accepted at C2, but status_busy remains set afterward. Rule to apply: status_busy clears only when the internal decoded pulse status_rd is asserted for an accepted read of address 0x30. Which signal should be traced next to test whether the clear decode fired?

Waveform for Clear-on-Read Status Bit Stays Set. Signals: valid, ready, addr, status_busy. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)