1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ145

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Q145DesignMetaASIC interview problem

Eight-bit scan-chain RTL

TechniquesDFTScanRTL DesignSystemVerilog

DifficultyMedium

TopicDFT

LanguageSystemVerilog

Requirements4 checkpoints

Problem

An eight-flop register supports functional parallel capture and serial scan shifting. Implement the scan behavior with a defined shift direction, reset, and observable serial output.

Starting declarationSystemVerilog

input  logic       clk, rst_n, scan_en, scan_in;
input  logic [7:0] func_d;
output logic [7:0] q;
output logic       scan_out;

Example input and output

Use this case to check your interpretation

Input

Before scan edge: q=8'hA5, scan_en=1, scan_in=0

Output

Before edge scan_out=1; after edge q=8'h4A

Explanation

Old q[7] is observed at scan_out, while the remaining bits shift toward bit 7 and zero enters bit 0.

Requirements (4)

With scan_en=1, load q[0] from scan_in and q[i] from prior q[i-1] for i=1 through 7.
Define scan_out as current q[7], making the pre-edge shifted-out bit observable.
With scan_en=0, capture func_d into all eight bits in parallel.
Use synchronous active-low reset; rst_n=0 on a rising edge clears q regardless of scan_en.