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DescriptionQ139
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Q139DVASIC interview problem

Request Exceeds Its Timeout

TechniquesDVWaveform Debugging
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

Each column is one rising clock edge. req and ack are one-cycle pulses, and busy marks the live pending window from request acceptance through its last allowed response edge. Rule to apply: After req rises, busy remains 1 while ack may arrive on any of the next three edges. The window closes after the third edge, so a later ack is a timeout. Which timeout assertion fails on this waveform?

Waveform for Request Exceeds Its Timeout. Signals: req, ack, busy. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)