DescriptionQ113
Q113DesignArchMetaASIC interview problem
Two-cycle valid pipeline
TechniquesDesignSystemVerilogPipelineValid
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A simple accelerator operation adds one to each accepted word and must report the result exactly two rising edges after the acceptance edge. Implement data and valid movement, bubbles, and reset behavior.
Starting declarationSystemVerilog
input logic clk, rst_n;
input logic in_valid;
input logic [15:0] in_data;
output logic out_valid;
output logic [16:0] out_data;Example input and output
Use this case to check your interpretationInput
in_valid=1, in_data=7 at acceptance edge C0Output
out_valid=1, out_data=8 at C2Explanation
The transformed word advances through slots 0, 1, and 2 while the valid bit follows the identical path.
02
Requirements (4)
- When in_valid is 1 at a rising edge, present in_data + 1 with out_valid 1 exactly two rising edges later.
- The interface has no backpressure; accept one input per cycle and preserve the order of back-to-back valid inputs.
- Propagate a cycle with in_valid 0 as a bubble that produces out_valid 0 two cycles later.
- When rst_n is 0 at a rising edge, clear all pipeline-valid state; data values during invalid cycles are ignored.