Hardware interview practice

Two-cycle valid pipeline

MediumRTL DesignSystemVerilog

A simple accelerator operation adds one to each accepted word and must report the result exactly two rising edges after the acceptance edge. Implement data and valid movement, bubbles, and reset behavior.

Starting point

Question code

input logic clk, rst_n;
input logic in_valid;
input logic [15:0] in_data;
output logic out_valid;
output logic [16:0] out_data;

Reviewed example

Work through one case

Input

in_valid=1, in_data=7 at acceptance edge C0

Expected output

out_valid=1, out_data=8 at C2

The transformed word advances through slots 0, 1, and 2 while the valid bit follows the identical path.

What to cover

Requirements

When in_valid is 1 at a rising edge, present in_data + 1 with out_valid 1 exactly two rising edges later.
The interface has no backpressure; accept one input per cycle and preserve the order of back-to-back valid inputs.
Propagate a cycle with in_valid 0 as a bubble that produces out_valid 0 two cycles later.
When rst_n is 0 at a rising edge, clear all pipeline-valid state; data values during invalid cycles are ignored.