DescriptionQ1050
Q1050DesignGoogleASIC interview problem
Average four accepted samples
TechniquesDesignSystemVerilogStreamingAccumulator
DifficultyEasy
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A streaming sensor needs the floor of the average of each non-overlapping group of four accepted unsigned samples. Implement synthesizable RTL for the four-sample averager.
Starting declarationSystemVerilog
input logic clk, rst_n;
input logic in_valid;
input logic [7:0] in_data;
output logic avg_valid;
output logic [7:0] avg;Example input and output
Use this case to check your interpretationInput
Accepted samples: 4, 8, 12, 16Output
avg=10 with one avg_valid pulse after sample 16Explanation
The 10-bit total is 40, and floor(40/4)=10. Idle cycles between accepted samples do not change the count.
02
Requirements (4)
- On each rising edge with in_valid=1, accept one sample; cycles with in_valid=0 do not advance the four-sample group.
- Use enough accumulator bits for four values of 255, and output floor(sum/4) for each non-overlapping group.
- Assert avg_valid for exactly the cycle after the edge that accepts the fourth sample; otherwise drive avg_valid=0.
- When rst_n=0 at a rising edge, synchronously discard any partial group, set avg_valid=0, and set avg=0.