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DescriptionQ104
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Q104DVASIC interview problem

Modulo Counter Fails to Wrap

TechniquesDVWaveform Debugging
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

count is a three-bit modulo-8 counter. en and load are sampled before each edge; count is shown immediately afterward, and load remains 0 throughout. Rule to apply: load has priority over en and would replace count with a programmed value. With load=0, en=1 increments modulo 8 and en=0 holds the prior count. Which assertion fails at C3?

Waveform for Modulo Counter Fails to Wrap. Signals: en, count, load. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)