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Hardware interview practice

Modulo Counter Fails to Wrap

EasyWaveform DebuggingSystemVerilog

count is a three-bit modulo-8 counter. en and load are sampled before each edge; count is shown immediately afterward, and load remains 0 throughout. Rule to apply: load has priority over en and would replace count with a programmed value. With load=0, en=1 increments modulo 8 and en=0 holds the prior count. Which assertion fails at C3?

Waveform for Modulo Counter Fails to Wrap. Signals: en, count, load. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. count must become 0 after an enabled edge from 7.
  2. B. load is high at C3, so count may legally remain 7.
  3. C. count must become 8 after an enabled edge from 7.
  4. D. en must become 0 before count reaches 7.