DescriptionQ1036
Q1036DVAppleASIC interview problem
Test 128 lines for stuck faults and pairwise shorts
TechniquesDVDesignDFTBoard validationSignature patterns
DifficultyHard
TopicFormal Verification
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Construct a deterministic pattern set for 128 independently driven and sampled digital lines that detects any single stuck-at fault and any pairwise short under the stated digital observation model.
Example input and output
Use this case to check your interpretationInput
Line 5 signature=0000101 and line 6 signature=0000110; apply the differing bit columns and their complementsOutput
The pair is commanded (0,1) in one pattern and (1,0) in its complement; a collapsing short produces a readback mismatch in at least one caseExplanation
Unique signatures guarantee at least one differing column for every pair, and complements reverse which endpoint is commanded high.
02
Requirements (4)
- Assign line i its unique seven-bit binary signature and apply each of the seven signature columns plus its complement, for exactly 14 drive patterns.
- Every line must be driven both 0 and 1, and every pair must be driven oppositely in both polarities in at least one original/complement column pair.
- Observation model: when two shorted lines are commanded oppositely, their sampled digital values collapse to the same 0 or 1, so at least one sampled line differs from its commanded bit; any such mismatch detects the short.
- State that real electrical contention may instead require current limits, analog thresholds, pull structures, or Hi-Z tests; the 14-pattern proof applies only to the defined observation model.