Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Test 128 lines for stuck faults and pairwise shorts

Hardware interview practice

Test 128 lines for stuck faults and pairwise shorts

HardFormal VerificationSystemVerilog

Construct a deterministic pattern set for 128 independently driven and sampled digital lines that detects any single stuck-at fault and any pairwise short under the stated digital observation model.

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Reviewed example

Work through one case

Input
Line 5 signature=0000101 and line 6 signature=0000110; apply the differing bit columns and their complements
Expected output
The pair is commanded (0,1) in one pattern and (1,0) in its complement; a collapsing short produces a readback mismatch in at least one case

Unique signatures guarantee at least one differing column for every pair, and complements reverse which endpoint is commanded high.

What to cover

Requirements

  1. Assign line i its unique seven-bit binary signature and apply each of the seven signature columns plus its complement, for exactly 14 drive patterns.
  2. Every line must be driven both 0 and 1, and every pair must be driven oppositely in both polarities in at least one original/complement column pair.
  3. Observation model: when two shorted lines are commanded oppositely, their sampled digital values collapse to the same 0 or 1, so at least one sampled line differs from its commanded bit; any such mismatch detects the short.
  4. State that real electrical contention may instead require current limits, analog thresholds, pull structures, or Hi-Z tests; the 14-pattern proof applies only to the defined observation model.
asic.fyi · Learn silicon end to end.info@asic.fyi