DescriptionQ1026
Q1026DVASIC interview problem
Verify pipeline reachability
TechniquesUVMOut-of-orderGreedy frontierReset epoch
DifficultyMedium
TopicUVM Components
LanguageSystemVerilog
Requirements5 checkpoints
01
Problem
Implement the predictor and tagged scoreboard core for a Universal Verification Methodology (UVM) testbench whose accelerator reports whether stage zero reaches the final stage and the furthest reachable index.
Example input and output
Use this case to check your interpretationInput
request id3 with stage_count=5 and advances=[2,0,2,0,0]Output
reachable=1; furthest_reachable_index=4Explanation
Clamped frontier progress reaches the final configured index; the prediction remains keyed by id3 if other responses reorder around it.
02
Requirements (5)
- Define advance[i] as the maximum number of stages that a request at stage i may move forward; clamp the resulting frontier to the final configured index.
- Treat count one as reachable and reject counts outside 1 through 16 with zeroed results.
- Store predictions by request ID, detect duplicate or unknown responses, and allow at most four outstanding requests.
- On reset, increment the scoreboard epoch and flush all pending predictions; reject responses with no live post-reset ID and explain the ambiguity of an old response that reuses a current ID.
- Add request and response ready/valid stability assertions; treat drivers, monitors, backpressure generation, and coverage as follow-up environment work.