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Hardware interview practice

Verify pipeline reachability

MediumUVM ComponentsSystemVerilog

Implement the predictor and tagged scoreboard core for a Universal Verification Methodology (UVM) testbench whose accelerator reports whether stage zero reaches the final stage and the furthest reachable index.

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Reviewed example

Work through one case

Input
request id3 with stage_count=5 and advances=[2,0,2,0,0]
Expected output
reachable=1; furthest_reachable_index=4

Clamped frontier progress reaches the final configured index; the prediction remains keyed by id3 if other responses reorder around it.

What to cover

Requirements

  1. Define advance[i] as the maximum number of stages that a request at stage i may move forward; clamp the resulting frontier to the final configured index.
  2. Treat count one as reachable and reject counts outside 1 through 16 with zeroed results.
  3. Store predictions by request ID, detect duplicate or unknown responses, and allow at most four outstanding requests.
  4. On reset, increment the scoreboard epoch and flush all pending predictions; reject responses with no live post-reset ID and explain the ambiguity of an old response that reuses a current ID.
  5. Add request and response ready/valid stability assertions; treat drivers, monitors, backpressure generation, and coverage as follow-up environment work.
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