DescriptionQ1015
Q1015DesignMetaASIC interview problem
Power-state transition controller
TechniquesDesignLow powerFSMRetention
DifficultyHard
TopicLow Power Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A block supports ACTIVE, RETENTION, and OFF. State must be saved before isolation, and an OFF block must wait for power_good before restore. Implement the controller for sleep, full power-off, and wake-up.
Starting declarationSystemVerilog
input logic clk, rst_n, sleep_req, off_req, wake_req, save_done, power_good;
output logic save, isolate, power_en, restore;Example input and output
Use this case to check your interpretationInput
State OFF, wake_req=1; power_good remains 0 for two cycles then becomes 1Output
POWER_UP holds power_en=1 and isolate=1; one RESTORE cycle follows power_good, then ACTIVE removes isolationExplanation
The explicit transient states prevent restore before power_good and prevent isolation release until restore has completed.
02
Requirements (4)
- ACTIVE drives power_en=1 and isolate=0; sleep_req enters SAVE and waits for save_done before RETENTION.
- RETENTION keeps power_en=1 and isolate=1; off_req enters OFF and lowers power_en, with no direct ACTIVE-to-OFF transition.
- Wake from RETENTION performs one RESTORE cycle; wake from OFF raises power, waits for power_good, then restores before returning ACTIVE.
- Synchronous active-low reset enters OFF with safe outputs, and sleep/off requests are ignored outside ACTIVE where specified.