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Part 1 · DFT and memory test

Flow handoffs, scan, ATPG, MBIST, and JTAG

Carry implementation intent through explicit handoffs, then trace controllability, capture, observability, compaction, memory test, and access ownership end to end.

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16 of 16 practice questions shown.

  1. Q1010Order the digital ASIC implementation flowFlow & signoff · EasySequence the digital ASIC flow and name each handoff artifact.Premium
  2. Q0080Order an RTL-to-GDS flowFlow & signoff · EasyOrder RTL-to-GDS stages by what each consumes, changes, and proves.Free
  3. Q0996Match a physical-signoff failure to its fixFlow & signoff · MediumMatch timing, IR/EM, DRC, LVS, and antenna failures to root-cause fixes.Premium
  4. Q0864Scan shift versus captureScan & ATPG · EasySeparate scan shift from functional capture mode and clocking.Premium
  5. Q0447Generate a scan shift-capture sequenceScan & ATPG · MediumConstruct a legal load, capture, and unload scan timeline.Premium
  6. Q0163Eight-bit scan-chain RTLScan & ATPG · MediumCode an 8-bit scan chain with correct scan-enable behavior.Free
  7. Q0993Find vectors that expose internal stuck-at faultsScan & ATPG · MediumActivate and propagate internal stuck-at faults to observable outputs.Premium
  8. Q0670Detect a transition-delay fault at speedScan & ATPG · MediumChoose launch and capture edges that expose transition-delay faults.Premium
  9. Q0502Model a four-bit MISR signatureScan & ATPG · MediumCompute a four-bit MISR recurrence and expected signature.Premium
  10. Q0392Contain unknowns before scan compactionScan & ATPG · MediumContain unknown responses before they poison scan compaction.Premium
  11. Q0556Drive a complete March C-minus memory testMemory & access · HardApply the complete March C− address and operation sequence.Premium
  12. Q0382Architect scan, MBIST, and JTAG accessMemory & access · HardPartition scan, MBIST, JTAG, and test-controller ownership.Premium
  13. Q0246Four-bit JTAG instruction registerMemory & access · MediumImplement JTAG instruction capture, shift, update, and decode.Free
  14. Q0317Choose a pattern for an adjacent-row disturb faultMemory & access · EasySelect an operation sequence that exposes adjacent-row disturbance.Premium
  15. Q0936Choose the operation that exposes a stuck-at-zero SRAM cellMemory & access · EasyChoose the read/write operation that reveals a stuck-at-zero cell.Premium
  16. Q1062Count unique detected faultsMemory & access · MediumCount unique detected faults without double-counting patterns.Premium

Implementation flowMove intent through every handoff

Treat RTL-to-GDS as a chain of explicit contracts. Each stage consumes design intent, changes the implementation, and produces evidence for the next owner.

Concept model

One implementation, seven evidence gates

  1. 01RTLconstraints
  2. 02Synthesis + DFTscan-ready netlist
  3. 03Floorplanplaced macros
  4. 04Place + CTStimed clocks
  5. 05Routerouted database
  6. 06Extractparasitics
  7. 07Signofftapeout evidence
Intent in
netlist · SDC · UPF · test protocol
Evidence out
reports · checks · waivers · reproducible database
Closure loop
violation → scoped ECO → re-analysis
Logic
RTL + SDCSynthesis maps behavior while preserving clocks, exceptions, and operating assumptions.
Test
scan-ready netlistTest insertion adds controllability and observability without changing functional behavior.
Physical
placed + routedFloorplan, clocks, cells, wires, and parasitics turn logical intent into geometry.
Release
signed evidenceTiming, power integrity, physical verification, and equivalence must agree on the released database.

Synthesis, test insertion, floorplanning, placement and clocking, routing, extraction, and signoff refine the same design. A handoff is complete only when the data and its assumptions travel together.

Strong answer

A complete handoff includes the design database, the constraints and intent used to interpret it, and evidence that the producing stage met an agreed acceptance contract.

Reason it through

  • Version the netlist or layout together with timing constraints, power intent, libraries, operating conditions, and tool settings.
  • Check for missing clocks, unconstrained paths, invalid exceptions, unresolved references, and inconsistent units before downstream work begins.
  • Record quality metrics, waivers, known limitations, and an owner for every open issue so assumptions do not become invisible.
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Strong answer

DFT architecture starts before synthesis, scan insertion usually operates on a synthesized test-ready netlist, and its added clocks, modes, chains, and timing paths remain part of physical implementation and signoff.

Reason it through

  • Plan scan partitions, compression, memory test, test clocks, and access logic early enough to affect RTL and floorplan decisions.
  • After insertion, prove functional equivalence in functional mode and run DFT-rule checks before placement consumes the netlist.
  • Reorder chains and optimize test routing during physical design, then regenerate or validate patterns against the final implementation assumptions.
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Strong answer

Routing creates geometry, but tapeout requires extracted electrical analysis, manufacturing-rule checks, connectivity agreement, reliability checks, and proof that late implementation changes preserved logic.

Reason it through

  • Final parasitics can expose timing and signal-integrity failures that early estimates did not predict.
  • DRC, LVS, antenna, density, IR-drop, and electromigration checks address risks that a routed database alone does not certify.
  • A release should tie all reports, waivers, netlists, layouts, and constraints to the exact final revision.
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Structural testControl, capture, and observe faults

Scan converts difficult sequential state into controllable and observable test state. ATPG still needs a sensitized path and a capture event that preserves the fault effect.

Concept model

Separate shift time from capture time

S0Shiftscan_en=1Load state
S1Shiftscan_en=1Load state
LLaunchscan_en=0Launch transition
CCapturescan_en=0Sample response
U0Unloadscan_en=1Observe state
U1Unloadscan_en=1Observe state

Illustrative launch-on-capture sequence; launch-on-shift changes the launch edge, not the activation–propagation–observation obligation.

ModelActivateObserveTargets
Stuck-atforce 0 or 1single capturelogical defect
Transitionlaunch edgeat-speed captureslow-to-rise/fall
Shift
SE = 1Serial clocks load stimulus and unload a prior response through each scan chain.
Capture
SE = 0Functional logic launches or samples the response on the defined test-clock edge.
Compact
many → fewResponse compactors reduce output volume but require deliberate handling of unknown values.
Diagnose
pattern + chainFailing cycles and chain positions help localize likely defect sites after detection.

Shift cycles load and unload scan state with scan enable asserted. One or more functional-speed capture edges launch and sample the response before the chain returns to shift mode.

Strong answer

Shift mode connects scan flops as serial chains to load and unload state. Capture mode restores the functional data paths so one or more controlled clock edges record the circuit response.

Reason it through

  • Scan enable and any compression controls must settle before the clock protocol changes modes.
  • Stuck-at patterns commonly use one capture edge, while transition patterns use launch and capture events at the intended functional speed.
  • The tester compares unloaded response bits with expected values after accounting for masked or intentionally unknown positions.
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Strong answer

ATPG drives the fault site to the opposite of the faulty value, chooses side inputs that sensitize a path, and propagates the resulting difference to a scan cell or observable output.

Reason it through

  • Activation, propagation, and observation are separate requirements; satisfying only one does not detect the fault.
  • Controlling values on reconvergent logic, sequential depth, X sources, and test constraints can block propagation.
  • Untestable and aborted faults should be classified by reason so a coverage gap can be accepted or repaired deliberately.
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Strong answer

A transition test launches a value change and captures its arrival using the functional-speed edge spacing, so excessive path delay can be observed as an incorrect sampled value.

Reason it through

  • Launch-on-capture and launch-on-shift protocols create different initialization and clock-control obligations.
  • The targeted path needs a valid transition, sensitized side inputs, and a capture point that remains visible through compaction.
  • Test clocks, clock gating, on-chip clock controllers, and tester timing must reproduce the intended launch-to-capture interval.
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Embedded testGive memories and test logic clear ownership

Memory BIST, scan compression, and JTAG solve different access problems. Their controllers, clocks, resets, and result paths must compose without contention.

Concept model

Route one test request to the right engine

External accessJTAG TAPinstruction + data registers
Logic testscan controllerchains · compression · ATPG
Memory testMBIST controlleraddress · data · compare
responseX-maskMISRexpected signature
  1. ⇕w0
  2. ⇑r0 · w1
  3. ⇑r1 · w0
  4. ⇓r0 · w1
  5. ⇓r1 · w0
  6. ⇕r0
Logic test
scan + ATPGChains expose sequential state so structural patterns can target random logic faults.
Memory test
March elementsOrdered reads and writes expose cell, transition, address, and coupling behaviors.
Compression
MISRA deterministic recurrence condenses response streams into a final signature.
Access
TAP / IJTAGInstructions select data registers or embedded instruments without giving two engines control at once.

A TAP or chip test controller selects an instrument. Scan logic tests random logic, MBIST applies memory-specific operations, and status returns through an owned, deterministic path.

Strong answer

An unknown entering a linear compactor can contaminate many signature bits and hide otherwise deterministic fault effects, so known X sources need masking, blocking, control, or bypass before compaction.

Reason it through

  • Common sources include uninitialized memories, analog boundaries, uncontrolled clocks, and nondeterministic functional state.
  • Masking protects observability but can reduce coverage, so ATPG must know which channels and cycles are unavailable.
  • X-bounding logic and masks need their own structural checks because a stuck mask can silently discard valid response data.
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Strong answer

A March test applies ordered read and write operations while traversing addresses in specified directions, creating the background and neighbor activity needed to expose cell, transition, address, and coupling faults.

Reason it through

  • Each read checks the value established by a previous element before the next write changes the background.
  • Ascending and descending passes exercise address order and opposite neighbor relationships.
  • The controller must define operation order, read latency, repair behavior, and the exact response used to set fail status.
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Strong answer

Scan and ATPG target random logic, MBIST applies memory-specific algorithms, and JTAG or an embedded-instrument network provides external access and selection. A chip test controller coordinates shared clocks, resets, modes, and status.

Reason it through

  • Every test instruction needs a defined data path, active controller, legal clock source, and exit sequence back to functional operation.
  • MBIST may own a memory interface during test, so isolation and muxing must prevent concurrent functional access.
  • Bypass, reset, and unsupported-instruction behavior should be deterministic so one instrument cannot strand another.
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