State, Power & Clock Integrity

task mac_driver::run_phase(uvm_phase phase);
  forever begin
    wait (vif.rst_n === 1'b1);

    fork
      begin : drive_process
        forever begin
          seq_item_port.get_next_item(req);
          drive_item(req);
          seq_item_port.item_done();
        end
      end

      begin : reset_watcher
        @(negedge vif.rst_n);
        uvm_report_info("DRV", "Reset detected: abort drive", UVM_LOW);
      end
    join_any

    disable fork;
    cleanup_signals();
  end
endtask

task mac_driver::cleanup_signals();
  vif.valid <= 1'b0;
  vif.data  <= 'z;
  // The reset handler kills the sequence, so this path does not call item_done().
endtask

The drive loop and reset watcher race. Reset wins immediately, disable fork removes stale drive activity, and the interface returns to an idle value before the next boot.

function void mac_scoreboard::flush();
  exp_fifo.flush();
  actual_fifo.flush();
  m_expected_count = 0;
endfunction

task mac_env::run_phase(uvm_phase phase);
  forever begin
    @(negedge vif.rst_n);

    agt.sqr.stop_sequences();
    scb.flush();
    reg_model.reset();

    wait (vif.rst_n === 1'b1);
    uvm_report_info("ENV", "Reset released: resume", UVM_LOW);
  end
endtask

Cleanup follows the hardware state transition: stop producers, discard predictions that no longer exist, synchronize the register mirror, then wait for reset release.

task power_aware_monitor::run_phase(uvm_phase phase);
  forever begin
    @(posedge vif.clk);

    if (!vif.pwr_good) begin
      handle_power_down_cleanup();
      wait (vif.pwr_good);
      wait (vif.init_complete);
    end
    else if (vif.valid && vif.ready) begin
      sample_transaction();
    end
  end
endtask

The functional monitor uses the externally visible availability contract to decide when transactions are meaningful. Separate always-on assertions continue checking isolation clamps and power sequencing throughout the off interval.

virtual function void update_ral_mirror(bit power_up);
  if (power_up) begin
    reg_model.volatile_block.reset("POWER");
    // reg_model.retention_block remains unchanged.
  end
endfunction

The model applies power-cycle defaults only to state that silicon actually loses.

property p_outputs_clamped_while_off;
  @(posedge aon_clk) disable iff (!por_n)
    !pwr_good |-> (island_outputs == SAFE_CLAMP_VALUE);
endproperty

assert property (p_outputs_clamped_while_off);

An always-on clock observes the boundary and proves that an unavailable island cannot drive an unsafe value into live logic.

task clk_gating_checker::run_phase(uvm_phase phase);
  logic gated_clk_previous;
  gated_clk_previous = vif.gated_clk;

  forever begin
    @(posedge vif.ref_clk);

    if (vif.idle_for_32_cycles) begin
      #1ps;
      if (vif.gated_clk !== gated_clk_previous)
        uvm_report_error("PWR_ERR", "Clock toggled during IDLE");
    end

    gated_clk_previous = vif.gated_clk;
  end
endtask

The always-on reference clock provides an observation point. The 1 ps offset avoids sampling in the same simulator region as the clock edge.

property p_clock_stable_while_disabled;
  @(posedge vif.ref_clk) disable iff (!vif.rst_n)
    !vif.clk_en |=> $stable(vif.gated_clk);
endproperty

assert property (p_clock_stable_while_disabled);

The production-safe invariant is stability, whether the implementation parks the gated clock at 0 or 1. A separate technology-specific assertion can require the actual park level.

// Gray Code pointers only change by 1 bit at a time
property p_gray_code_continuity(ptr);
  @(posedge clk)
  $changed(ptr) |->
    ($countones(ptr ^ $past(ptr)) == 1);
endproperty

assert_wr_ptr_gray: assert property (
  p_gray_code_continuity(vif.wr_ptr_gray)
);

assert_rd_ptr_gray: assert property (
  p_gray_code_continuity(vif.rd_ptr_gray)
);

The XOR identifies changed pointer bits and $countones requires exactly one when the pointer changes. The property is applied to both write and read Gray pointers.

property p_data_stability_during_cdc;
  @(posedge clk_src)
  disable iff (!vif.rst_n)
  $rose(vif.req) |->
    $stable(vif.data_bus) until_with (vif.ack);
endproperty

assert_cdc_data_stable: assert property (
  p_data_stability_during_cdc
)
else
  `uvm_error(
    "CDC_DATA",
    "Data bus toggled during active handshake!"
  );

After Request rises, the bundled data must remain stable through the cycle in which Ack completes the transfer.

interface cdc_if(input clk_src, input clk_dest);
  logic req;
  logic ack;
  logic [31:0] data;

  // Source Clocking Block: Driving logic
  clocking src_cb @(posedge clk_src);
    default input #1step output #100ps;
    output req, data;
    input ack;
  endclocking

  // Destination Clocking Block: Sampling logic
  clocking dest_cb @(posedge clk_dest);
    default input #200ps output #1step;
    input req, data;
    output ack;
  endclocking
endinterface

The source drives req/data and samples ack; the destination samples req/data and drives ack. The slide labels 100 ps source output skew and 200 ps destination input skew.

initial begin
  clk_dest = 0;
  forever begin
    // 1000ps base period (1GHz)
    // Add +/- 50ps of jitter every loop iteration
    int jitter = $urandom_range(0, 100) - 50;
    #((1000 + jitter) / 2.0 * 1ps);
    clk_dest = ~clk_dest;
  end
end

Every half-cycle uses a 1,000 ps nominal full-period value plus a random integer from -50 ps through +50 ps before division by two.