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The ground moves

State, Power & Clock Integrity

Keep the testbench and architectural model coherent while reset, power, clock, and domain boundaries change underneath in-flight work.

The ground movesThe shared verification responsibilities
  1. 01RUNObserve valid architectural state
  2. 02DISRUPTReset, gate a clock, or remove power
  3. 03CONTAINKill, clamp, flush, preserve, or pause
  4. 04RECOVERRelease only after initialization is valid

Reset recovery · Power gating · Clock gating · CDC DV

Choose exactly what to kill, flush, preserve, pause, isolate, restart, and prove at every lifecycle boundary.

The case library

Start with a failure.

Pick a mechanism. Open an experiment.

4 case studies

Mid-test resetDoes old work survive reset?
Failure to investigateState & power

Mid-Test Reset Orchestration

A driver completes a stale handshake or leaves valid asserted across reset.

Enter the lab ↗
Power gatingRelease isolation too early.
Failure to investigateState & power

Power Gating, Isolation, and Retention

An output is not clamped while its source island is off.

Enter the lab ↗
Clock gatingWhich edge accepts the transfer?
Failure to investigateState & power

Clock Gating and Wake-Up Integrity

The gated clock continues toggling after the IP satisfies its idle threshold.

Enter the lab ↗
Clock crossingsMove the clocks. Hold the data.
Failure to investigateState & power

CDC & RDC Dynamic Verification

Request changes again before acknowledgement and the destination loses or duplicates an event.

Enter the lab ↗
Practice with real interview promptsPractice this verification family in the question bank

Continue the evidence chain

Connect cases to system strategy.

Move from focused failure modes to a complete plan, executable architecture, coverage model, regression system, and sign-off argument.