1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

Question bank1110 results

Search questions

Filter by difficultyFilter by disciplineFilter by targeted interviewFilter by topicFilter by progress

DescriptionQ529

Q529DVASIC interview problem

Events

TechniquesSystemVerilogCommunication primitives

DifficultyEasy

TopicVerification Utilities

LanguageSystemVerilog

Format4 choices

What happens?

Starting declarationSystemVerilog

event done;
initial begin
  @done;
  $display("seen at %0t", $time);
end
initial #2 -> done;