DescriptionQ908
Q908DesignQualcommASIC interview problem
Detect Overlapping 1011 Sequences
TechniquesDesignFSM
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A serial checker samples one bit on each cycle with bit_valid=1 and must detect every overlapping occurrence of 1011. Implement the sequence detector and its exact idle, overlap, and reset behavior.
Module declarationSystemVerilog
module detect_1011(
input logic clk,rst_n,bit_valid,bit_in,
output logic detect_pulse
);Example input and output
Use this case to check your interpretationInput
Case 1: Scenario: Accepted bits 1,0,1,1 produce one pulse on the fourth accepted bit.
Case 2: Scenario: Accepted bits 1,0,1,1,0,1,1 produce pulses on accepted bits 4 and 7.
Case 3: Accepted bits 1,0,invalid,1,1 still form one match because the invalid cycleOutput
Case 1: Expected behavior: Accepted bits 1,0,1,1 produce one pulse on the fourth accepted bit.
Case 2: Expected behavior: Accepted bits 1,0,1,1,0,1,1 produce pulses on accepted bits 4 and 7.
Case 3: Holds state and is not a sampled bit.Explanation
The shown result follows by applying this rule: States encode the longest matched prefix of lengths zero through three, with complete next-state transitions. The cases also demonstrate this requirement: After a match, retain the longest suffix that is also a prefix of 1011 so a following accepted bit can participate in the next match.
02
Requirements (4)
- Use an active-low synchronous reset that returns to no matched prefix and clears detect_pulse.
- Advance state only on bit_valid; invalid cycles hold the matched-prefix state and produce no pulse.
- Pulse detect_pulse for one cycle when an accepted bit completes 1011, including overlapping matches, and clear it by default on the next cycle.
- After a match, retain the longest suffix that is also a prefix of 1011 so a following accepted bit can participate in the next match.