1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ090

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Q090DesignDVAMDASIC interview problem

Implement and Verify a Two-Input XOR

TechniquesDesignDigital logic

DifficultyEasy

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A parity helper needs a purely combinational two-input exclusive-OR output. Write the XOR RTL, truth table, and equivalent sum-of-products expression.

Module declarationSystemVerilog

module xor2(
 input logic A,B,
 output logic Y
);

Example input and output

Use this case to check your interpretation

Input

Case 1: A=0,B=0
Case 2: A=0,B=1
Case 3: A=1,B=1

Output

Case 1: Gives Y=0.
Case 2: Gives Y=1.
Case 3: Gives Y=0.

Explanation

The shown result follows by applying this rule: The operator, sum-of-products expression, and four-row table are mutually equivalent. The cases also demonstrate this requirement: Verify all four two-state input combinations and do not treat X or Z as a required Boolean truth-table value.

Requirements (4)

Implement Y as `A ^ B` using combinational RTL with no storage.
Give the complete input order 00,01,10,11 and output sequence 0,1,1,0.
State the equivalent Boolean expression `(~A & B) | (A & ~B)`.
Verify all four two-state input combinations and do not treat X or Z as a required Boolean truth-table value.