DescriptionQ860
Q860DesignQualcommASIC interview problem
Cross a burst count with a Gray counter
TechniquesDesignCDCResetCrosscounter
DifficultyMedium
TopicCDC & RDC
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A fast source may produce several events between destination edges. The destination needs the modulo-16 event delta, not one pulse per source event. Design the dual-clock SystemVerilog counter crossing.
Starting declarationSystemVerilog
input logic src_clk, src_rst_n, src_event;
input logic dst_clk, dst_rst_n;
output logic [3:0] dst_delta;
output logic [3:0] dst_total;Example input and output
Use this case to check your interpretationInput
The prior settled destination sample is binary 3, the new synchronized Gray sample decodes to 6, and dst_total is 9.Output
dst_delta=3 and the registered dst_total becomes 12 modulo 16.Explanation
Four-bit subtraction computes 6-3=3, and the destination accumulates that same delta on the sampling edge.
02
Requirements (4)
- Increment a 4-bit source binary count on each src_event and continuously derive its Gray-code value.
- Synchronize each Gray bit through two destination flip-flops, convert the synchronized Gray value back to binary, and compute modulo-16 delta from the prior destination sample.
- Accumulate dst_total modulo 16 and present dst_delta for each destination cycle; a stable source count yields delta zero after synchronization settles.
- Assume fewer than 8 source events occur between settled destination samples and constrain physical Gray-bus skew below one source period; both resets are asserted together and clear all state.