DescriptionQ825
Q825DVASIC interview problem
Verify a RAL-programmed grid checker
TechniquesUVM RALError precedenceInterruptBus protocol
DifficultyMedium
TopicUVM Components
LanguageSystemVerilog
Requirements5 checkpoints
01
Problem
Write the functional oracle and core bus/interrupt assertions for a memory-mapped 9-by-9 grid checker. A full Universal Verification Methodology Register Abstraction Layer (UVM RAL) environment is a follow-up discussion.
Example input and output
Use this case to check your interpretationInput
program grid cell(0,0)=12 through RAL, then accept STARTOutput
symbol violation at row0,column0; all result registers update atomically and done_irq pulses onceExplanation
Symbol values 10..15 have highest same-cell precedence, so row/column/region checks cannot replace this first error.
02
Requirements (5)
- Scan row-major, ignore zero, reject symbols 10 through 15, and apply same-cell precedence symbol, row, column, then region.
- Model one pending read: an accepted read responds one cycle later and holds data under backpressure; writes produce no read response.
- An idle START clears old status and errors, then completion updates all result registers atomically and pulses done_irq once; busy cell or START writes are rejected while status reads remain legal.
- Reset cancels checking and stalled reads, clears cells and result registers, suppresses interrupts, and is covered during programming, checking, and response stall.
- Explain separately how a RAL predictor would own mirror updates for accepted frontdoor traffic; it is not part of the code requested here.