DescriptionQ819
Q819DesignArchGoogleASIC interview problem
Build a two-stage elastic packet pipe
TechniquesDesignSystemVerilogReady-validElastic pipeline
DifficultyHard
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A packet stream needs two registered storage stages and must tolerate arbitrary downstream backpressure without loss, duplication, or reordering. Implement a two-entry elastic pipeline for data and last.
Starting declarationSystemVerilog
input logic clk, rst_n;
input logic in_valid; output logic in_ready;
input logic [31:0] in_data; input logic in_last;
output logic out_valid; input logic out_ready;
output logic [31:0] out_data; output logic out_last;Example input and output
Use this case to check your interpretationInput
The stages contain A then B, out_ready=1, and input C is valid on edge E0Output
A retires at E0; after E0 the registered order is B then CExplanation
The downstream stage is allowed to advance, so B shifts to the output stage while C replaces B in the input stage on the same edge.
02
Requirements (4)
- Accept input only when in_valid and in_ready are both 1, and retire output only when out_valid and out_ready are both 1.
- Provide exactly two registered entries, preserve order, and permit a simultaneous pop and push when full; an item accepted into an empty pipe at E0 becomes visible after E1.
- While out_valid=1 and out_ready=0, keep out_valid, out_data, and out_last stable and never overwrite the blocked item.
- Asserting rst_n=0 asynchronously empties both entries; after synchronous reset release no output is valid until a new item traverses the pipe.