1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ804

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Q804ArchIntelASIC interview problem

Verify predictor rollback after a misprediction

TechniquesArchCPU

DifficultyHard

TopicComputer Architecture

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A speculative branch predictor may update at prediction time but must repair or discard wrong-path state after a redirect. Design a reference model, checks, and coverage for rollback behavior.

Starting declarationSystemVerilog

predict: fetch_id, pc, predicted_taken, target
resolve: fetch_id, actual_taken, target
commit: fetch_id
flush: new_epoch
reset_n

Example input and output

Use this case to check your interpretation

Input

Case 1: IDs 10,11,12 predict; ID 10 mispredicts
Case 2: Two PCs alias one table entry, but only the committed path
Case 3: Reset during an unresolved branch

Output

Case 1: IDs 11 and 12 are killed.
Case 2: Determines final modeled state.
Case 3: Clears model and DUT predictor-valid state.

Explanation

The shown result follows by applying this rule: Fetch IDs and epochs prevent wrong-path events from matching new work. The cases also demonstrate this requirement: Cover correct/mispredicted direction, target miss, aliasing, rollback depth, and resolution order.

Requirements (4)

Track every prediction by fetch ID and epoch, and compare direction and target against a separate predictor model.
On flush, discard all younger wrong-path entries and prevent their speculative updates from becoming committed state.
Test nested branches, aliasing PCs, delayed resolution, back-to-back redirects, and reset coincident with resolve.
Cover correct/mispredicted direction, target miss, aliasing, rollback depth, and resolution order.