Skip to the selected question
ASIC.FYI

ASIC Question Bank

1,000+ hardware interview questions
DescriptionQ794
Page ↗
Q794DVASIC interview problem

Factory-aware component construction

TechniquesUVMClass roles and construction
DifficultyMedium
TopicUVM Components
LanguageSystemVerilog
Format4 choices
01

Problem

A test installs a type override from base_agent to coverage_agent before the environment is built, but the instantiated agent is still base_agent. What is the decisive defect?

Class declarationSystemVerilog
class env extends uvm_env;
  base_agent agt;
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    agt = new("agt", this);
  endfunction
endclass
02

Answer choices (4)