DescriptionQ736
Q736DesignIntelASIC interview problem
One-outstanding-event CDC handshake
TechniquesDesignCDCResetOne-Outstanding-EventCdc
DifficultyMedium
TopicCDC and Reset
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A source clock sends events to an unrelated destination clock. At most one event may be in flight. Design synthesizable SystemVerilog for a request/acknowledge event crossing.
Starting declarationSystemVerilog
input logic src_clk, src_rst_n, src_valid;
output logic src_ready;
input logic dst_clk, dst_rst_n;
output logic dst_pulse;Example input and output
Use this case to check your interpretationInput
Accept one source event while dst_clk runs four times slower than src_clk.Output
The destination produces exactly one dst_pulse.Explanation
The request toggle persists until its synchronized acknowledgement returns, so the slower domain cannot miss or duplicate the event.
02
Requirements (4)
- Accept an event only on src_valid && src_ready; while src_valid&&!src_ready the source must keep src_valid asserted, and the crossing must hold its request or toggle until acknowledgement returns.
- Generate exactly one destination-clock pulse for each accepted event and accept no second event while one is pending.
- Every signal crossing a clock boundary must pass through two destination-domain flip-flops before use.
- Both resets must be asserted together for at least two edges of each clock; during reset, clear the handshake and drive src_ready=0 and dst_pulse=0, then recover without a phantom event.