1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ716

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Q716DVIntelASIC interview problem

Verify an AHB-to-APB bridge

TechniquesDVDesignUVMAMBA

DifficultyMedium

TopicUVM

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A single-master, 32-bit AHB-Lite slave bridge translates naturally aligned byte, halfword, and word accesses to a 32-bit APB4 bus. The mapping is little-endian. Unsupported or unaligned accesses return AHB ERROR and create no APB transfer. Design the predictor, checks, tests, and coverage for the bridge.

Starting declarationSystemVerilog

AHB-Lite: HADDR, HTRANS, HWRITE, HSIZE, HWDATA[31:0], HRDATA[31:0], HREADYin, HREADYout, HRESP
APB4: PADDR, PSEL, PENABLE, PWRITE, PWDATA[31:0], PSTRB[3:0], PRDATA[31:0], PREADY, PSLVERR
active-low synchronous reset

Example input and output

Use this case to check your interpretation

Input

Case 1: Accept an aligned word write
Case 2: Hold PREADY low for three cycles
Case 3: Assert PSLVERR on completion

Output

Case 1: capture its later HWDATA, drive PSTRB=4'b1111, and create one APB SETUP followed by ACCESS until PREADY
Case 2: PADDR, PWRITE, PWDATA, and PSTRB remain stable
Case 3: drive HRESP=1/HREADYout=0, then HRESP=1/HREADYout=1 for exactly one completed AHB error response

Explanation

The shown result follows by applying this rule: The predictor separates the AHB address/control phase from the following write-data phase and models APB timing. The cases also demonstrate this requirement: Test sizes, back-to-back AHB requests, long APB waits, illegal decode, and reset during idle and ACCESS.

Requirements (4)

Capture address/control on an accepted AHB address phase (HREADYin && HTRANS[1]); for a write, capture HWDATA in its following data phase. Predict one APB SETUP and ACCESS, with PSTRB derived from HSIZE and HADDR[1:0].
Assert APB address, direction, select, write data, and byte strobes stay stable while PENABLE && !PREADY.
Map APB read data normally. For PSLVERR or an unsupported/unaligned request, use the standard two-cycle AHB-Lite ERROR response: HRESP=1 with HREADYout=0 in the first error cycle, then HRESP=1 with HREADYout=1 to complete; create no APB transfer for a locally rejected request.
Test sizes, back-to-back AHB requests, long APB waits, illegal decode, and reset during idle and ACCESS.