1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ659

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Q659DVASIC interview problem

Verify a tagged grid-path counter

TechniquesDVOut-of-orderDynamic programming

DifficultyMedium

TopicReference Models

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Verify an accelerator with up to four tagged, outstanding requests that counts right-or-down paths through a rectangular grid and may return responses out of order.

Interface declarationSystemVerilog

interface paths_if(input logic clk);
  logic rst_n, req_valid, req_ready;
  logic [3:0] req_id;
  logic [4:0] rows, cols;
  logic rsp_valid, rsp_ready;
  logic [3:0] rsp_id;
  logic rsp_error;
  logic [63:0] path_count;
endinterface

Example input and output

Use this case to check your interpretation

Input

accept id2 grid=2x3 and id7 grid=3x3; responses return id7 then id2

Output

id7 path_count=6 PASS; id2 path_count=3 PASS

Explanation

The 64-bit dynamic-programming oracle is keyed by request ID, so reversed response order remains legal.

Requirements (4)

For dimensions 1 through 16, predict in 64 bits with one on the top and left edges and upper-plus-left in every interior cell.
Track at most four unique outstanding req_id values and compare each response by ID rather than acceptance order.
Unknown, repeated, or stale responses fail; invalid dimensions return an error and zero path count.
Bound response latency, hold stalled responses stable, cancel all outstanding work on reset, and delay old-ID reuse long enough to expose late replies.