DescriptionQ602
Q602DVIntelASIC interview problem
Prove a register implements twelve data bits
TechniquesDVUVMRegisters
DifficultyHard
TopicUVM
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A 32-bit MMIO register implements DATA[11:0]. Bits [31:12] are read-as-zero and write-ignored. Write a UVM RAL test that proves the field width and reserved-bit behavior.
Starting declarationSystemVerilog
register DATA_REG at offset 0x20
implemented field DATA[11:0]: RW
reserved [31:12]: RAZ/WI
32-bit frontdoor bus
reset value = 0Example input and output
Use this case to check your interpretationInput
Case 1: Write 0x00000FFF
Case 2: Clear the register, then write 0xFFFFF000
Case 3: Write 0xABCDE123Output
Case 1: the readback is 0x00000FFF
Case 2: the readback is 0x00000000
Case 3: the readback is 0x00000123Explanation
The shown result follows by applying this rule: Model metadata and real frontdoor behavior are both checked. The cases also demonstrate this requirement: Write 32'hABCDE123 and read back 32'h00000123; report bus-status failures separately from compare failures.
02
Requirements (4)
- Check that the RAL model contains one 12-bit RW field at bit 0 and the stated reset value.
- Frontdoor-write 32'h00000FFF and read back 32'h00000FFF.
- Clear DATA, write 32'hFFFFF000, and read back zero to prove reserved bits are write-ignored/read-zero.
- Write 32'hABCDE123 and read back 32'h00000123; report bus-status failures separately from compare failures.