DescriptionQ557
Q557DVMicronASIC interview problem
Assert four-cycle spacing between activates to one bank
TechniquesAssertions & FormalAssertions / Formalassert four-cycle spacing between activates to one bank
DifficultyEasy
TopicAssertions & Formal
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A simplified memory interface forbids a second ACT to the same bank on the next three clocks after an accepted ACT. Write SystemVerilog assertions for all four banks.
Starting declarationSystemVerilog
input logic clk, rst_n;
input logic act_valid;
input logic [1:0] bank;Example input and output
Use this case to check your interpretationInput
An ACT to bank 1 occurs at C0 and another ACT to bank 1 occurs at C3.Output
The bank-1 spacing assertion fails at C3.Explanation
Offsets C1 through C3 are the three forbidden cycles after the first ACT; the same bank becomes legal again only at C4.
02
Requirements (4)
- Sample on rising clk edges and disable the checks while rst_n=0.
- If bank b has ACT at C0, another ACT to b is forbidden at C1, C2, and C3 and is legal again at C4.
- ACT commands to any other bank remain legal during those three cycles.
- Use a generate loop or equivalent per-bank property with a failure message that identifies the bank.