1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ528

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Q528ArchDVIntelASIC interview problem

Debug a Queue That Advances While Stalled

TechniquesDVDesignRTL debug

DifficultyMedium

TopicMemory Systems

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A queue passes all tests when out_ready is always high but loses data under backpressure. The read pointer update shown below is the first divergence from the reference queue. Verify the failure, repair the transfer condition, and add a regression that prevents recurrence.

Starting declarationSystemVerilog

assign out_valid = (count != 0);
assign out_data  = mem[rptr];
always_ff @(posedge clk) begin
  if (!rst_n) rptr <= '0;
  else if (out_valid) rptr <= rptr + 1'b1; // faulty
end

Example input and output

Use this case to check your interpretation

Input

Case 1: Queue A,B and hold ready low for two cycles
Case 2: Raise ready while A is valid
Case 3: Assert reset during a stall

Output

Case 1: faulty RTL displays A then B; repaired RTL holds A for both cycles
Case 2: exactly one pop occurs and B may appear after the accepting edge
Case 3: the queue empties, out_valid drops, and no pre-reset item is later reported as transferred

Explanation

The shown result follows by applying this rule: The debug method locates the first pointer/reference-queue divergence rather than only observing the final missing packet. The cases also demonstrate this requirement: Add an assertion for stable stalled output and a scoreboard test that applies randomized ready gaps, then retain the smallest failing seed as a regression.

Requirements (4)

Reproduce with a nonempty queue and out_ready=0 for at least two cycles; identify that out_data changes because rptr advances without a transfer.
Define pop as out_valid&&out_ready and advance rptr and decrement count only on pop, with simultaneous push/pop handled by the existing queue contract.
Active-low synchronous reset clears rptr, wptr, and count so both queue ends realign; while out_valid&& !out_ready, out_valid and out_data must remain stable and no item may be removed.
Add an assertion for stable stalled output and a scoreboard test that applies randomized ready gaps, then retain the smallest failing seed as a regression.