1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ501

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Q501FWArchAppleASIC interview problem

Measure dependent L1-cache load latency

TechniquesArchFWCPUL1 cacheMicrobenchmark

DifficultyHard

TopicMemory Systems

LanguageC

Requirements4 checkpoints

Problem

Design a C microbenchmark that estimates dependent-load latency for a 32 KiB L1 data cache. Explain how you prevent the compiler, prefetching, migration, and timer overhead from invalidating the result.

Starting declarationC

double measure_l1_cycles_per_load(
    uintptr_t **pointer_chain,
    size_t chain_bytes,
    size_t iterations);

Example input and output

Use this case to check your interpretation

Input

100000 dependent loads; serialized elapsed time 402000 cycles; matched empty-loop/timer overhead 2000 cycles; start/end CPU IDs match

Output

(402000-2000)/100000 = 4.0 cycles per dependent L1 load; accept the trial

Explanation

Dependency prevents parallel loads from hiding latency, and subtracting matched overhead isolates the approximate per-load cost.

Requirements (4)

Use an L1-sized randomized dependent pointer chain so each load supplies the address of the next load.
Warm the chain, keep the final pointer observable, and prevent compiler removal or reordering of the measured loop.
Use architecture-supported serialized cycle reads, subtract measured loop/timer overhead, and divide by accepted dependent loads.
Repeat trials, reject migration or non-L1 working sets, pin the thread when supported, and report a robust statistic such as the median.