1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ497

Q497DesignArchIntelASIC interview problem

Select the oldest ready micro-operation

TechniquesRTL DesignRTL / Microarchitectureselect the oldest ready micro-operation

DifficultyMedium

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

An eight-entry issue queue exposes valid, ready, and age fields. Age 0 is oldest. Write combinational SystemVerilog that selects one entry.

Starting declarationSystemVerilog

parameter int N=8;
input logic [N-1:0] valid, ready;
input logic [7:0] age [N];
output logic grant_valid;
output logic [$clog2(N)-1:0] grant_idx;

Use this case to check your interpretation

Input

valid=ready=8'b0010_1000, age[3]=5, and age[5]=2.

Output

grant_valid=1 and grant_idx=5.

Explanation

Entries 3 and 5 are eligible, and entry 5 has the smaller unsigned age value, so it is the oldest ready operation.

Eligible entries are exactly those with valid[i] && ready[i].
Choose the eligible entry with the smallest unsigned age value; if ages tie, choose the lower index.
When no entry is eligible, set grant_valid=0 and grant_idx=0.
Use complete combinational logic with no state; this is not a ready/valid transfer channel, so there is no backpressure and outputs need be stable only while inputs are stable.