DescriptionQ420
Q420DesignAMDASIC interview problem
Minimize a Four-Input Sum of Minterms
TechniquesDesignLogic optimization
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A combinational output is specified as F(A,B,C,D)=sum m(1,3,5,7,8,9,10,11,12,13,14,15), with A as the minterm MSB. Cost is two-input gate count, then literal count. Design the minimum expression, implement it, and prove equivalence for all inputs.
Module declarationSystemVerilog
module min_func(
input logic A,B,C,D,
output logic F
);Example input and output
Use this case to check your interpretationInput
Case 1: A=0,D=1
Case 2: A=1,D=0
Case 3: A=0,D=0Output
Case 1: Gives F=1 for any B,C, covering minterms 1,3,5,7.
Case 2: Gives F=1 for any B,C, including minterms 8,10,12,14.
Case 3: Gives F=0 for any B,C, matching minterms 0,2,4,6 outside the on-set.Explanation
The shown result follows by applying this rule: The algebra or Karnaugh map reaches A + ~A D = A + D. The cases also demonstrate this requirement: Exhaustively compare the implementation against the stated 16-row minterm function.
02
Requirements (4)
- Group minterms 8 through 15 as A and minterms 1,3,5,7 as ~A&D, then apply absorption.
- Implement the reduced expression F=A|D with one two-input OR gate and no dependence on B or C.
- Use purely combinational logic with a complete assignment and no clock, reset, latch, or unknown-as-don't-care assumption.
- Exhaustively compare the implementation against the stated 16-row minterm function.