1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ028

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Q028DVASIC interview problem

Synchronize a one-outstanding producer and consumer

TechniquesDVSystemVerilogMailboxSynchronizationProducer-consumer

DifficultyMedium

TopicTestbench Concurrency

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Implement two finite testbench threads in which the producer may send the next packet only after the consumer acknowledges the previous one. Consumer processing takes 0 through 5 clocks.

Producer-consumer sequence using depth-one data and acknowledgement mailboxes to keep at most one packet outstanding. — A persistent acknowledgement token releases the producer only after the consumer finishes the current packet.

Starting declarationSystemVerilog

mailbox #(packet) data_mb = new(1);
mailbox #(bit)    ack_mb  = new(1);

Example input and output

Use this case to check your interpretation

Input

consumer delay = 5 clocks for every packet

Output

packet IDs 0 through 9 are received once in order, with at most one packet outstanding

Explanation

The producer blocks on ack_mb.get() after every put, so it cannot enqueue the next packet until the consumer completes the prior one.

Requirements (4)

Block the producer after each data put until one acknowledgment is received.
Have the consumer receive one packet, wait 0 through 5 clocks, and send exactly one acknowledgment.
Transmit packet IDs 0 through 9 exactly once and wait for both threads to finish.
Use persistent mailbox tokens rather than a bare event whose trigger could be missed.