1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ027

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Q027DVASIC interview problem

Verify a mirrored topology checker

TechniquesDVTreesValidationLatencyCoverage

DifficultyMedium

TopicReference Models

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Verify a bounded level-order tree checker that distinguishes value asymmetry, shape asymmetry, and malformed ancestry.

Level-order binary tree showing matching mirror pairs and a malformed case with a valid child under an invalid parent. — Map each node to its mirror partner, then check ancestry validity separately from value symmetry.

Starting declarationSystemVerilog

logic clk, rst_n, start;
logic [4:0] node_count;
logic [30:0] node_valid;
logic [7:0] node_value [31];
logic busy, done, request_error, symmetric;
parameter int MAX_LATENCY = 40;

Example input and output

Use this case to check your interpretation

Input

node_count=7; valid bits all set; level-order values=[1,2,2,3,4,4,3]

Output

well_formed=1; symmetric=1

Explanation

Every nonroot node has a valid parent, and mirror pairs match in both presence and value at each level.

Requirements (4)

Use child indexes 2*i+1 and 2*i+2 below node_count, with no valid bits at indexes greater than or equal to node_count.
Require a valid root for a nonempty tree and a valid parent for every valid nonroot node.
Compare every same-level mirror pair for both presence and value without reading invalid-node data.
Return a fixed malformed-input result and require one bounded completion unless reset cancels it.