1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ222

Page ↗

Q222DesignDVAppleASIC interview problem

Check divisibility by five on an LSB-first bit stream

TechniquesDesignDVFSMModuloBackpressure

DifficultyMedium

TopicStreaming RTL

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Receive one LSB-first bit per accepted cycle and report whether each nonempty framed unsigned value is divisible by five. An abort input must discard a partial frame without producing a result.

Module declarationSystemVerilog

module div5_stream (
  input logic clk, rst_n, abort,
  input logic in_valid, in_bit, in_last,
  output logic in_ready,
  output logic out_valid, div_by_5,
  input logic out_ready
);

Example input and output

Use this case to check your interpretation

Input

Accept bits 1,0,1 with in_last on the third bit; later accept 1,1, abort, then start a new frame 0,1,1

Output

First result div_by_5=1 because 101 LSB-first is 5; aborted frame has no result; final result is 0 because 011 LSB-first is 6

Explanation

LSB-first framing requires tracking the current power-of-two weight modulo five. Abort explicitly resets that weight as well as the accumulated remainder.

Requirements (4)

Treat the first accepted bit as position zero, with remainder r=0 and current weight w=1.
On each handshake update r=(r+in_bit*w)%5 and w=(2*w)%5; include the in_last bit in the published result.
Hold out_valid and div_by_5 stable under output backpressure and accept no next-frame input until the result is consumed.
Give abort priority over input: it discards partial state, clears any pending output, restores r=0/w=1, and emits no result.