1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ1054

Q1054DesignDVNVIDIAASIC interview problem

Detect the wildcard pattern 110?01

TechniquesDesignDVSystemVerilogFSMPattern detector

DifficultyHard

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

Implement both an overlapping FSM and a six-bit shift-register detector for 110?01, where ? is either binary value. Make their outputs agree.

Starting declarationSystemVerilog

input logic clk, rst_n, in_bit;
output logic detect_fsm, detect_shift;

Use this case to check your interpretation

Input

Streams 110001, 110101, and 110111

Output

First two match on bit 6; the third does not

Explanation

The fourth bit may be 0 or 1, but the required fifth bit must be 0.

Sample one binary input per rising edge and pulse on the final bit.
Treat ? as a don't-care pattern position, not four-state X.
Suppress detection until six bits have been sampled after reset.
Preserve compatible prefix state for overlapping matches and assert both implementations agree.