DescriptionQ1029
Q1029DesignAMDASIC interview problem
Floorplan a four-bank SRAM subsystem
TechniquesDesignDDRMemoryArbitration
DifficultyMedium
TopicPhysical Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A block contains four SRAM macros, request arbitration, address decode, and one output mux. Design a block floorplan and explain the timing, routing, and power trade-offs.
Starting declarationSystemVerilog
4 equal SRAM macros
central request arbiter
address decoder
4-to-1 output mux
shared clock/reset
block power gridExample input and output
Use this case to check your interpretationInput
Case 1: Use a 2×2 macro arrangement with a central channel
Case 2: Place every output pin away from the mux
Case 3: Make the channel too narrow for signals plus power strapsOutput
Case 1: address distribution is regular
Case 2: the return-data path grows and the floorplan is rejected
Case 3: flag the issue before placementExplanation
The shown result follows by applying this rule: The floorplan is physically routable, not just a logical block diagram. The cases also demonstrate this requirement: State one trade-off among macro proximity, wire delay, congestion, power-grid continuity, and usable placement area.
02
Requirements (4)
- Place macros regularly with pins facing nearby decode/mux logic where the macro pinout permits.
- Reserve routing channels and continuous power straps; avoid narrow notches and blocked pin access.
- Identify the address/control spine, clock/reset distribution, and the output-mux path as timing/congestion risks.
- State one trade-off among macro proximity, wire delay, congestion, power-grid continuity, and usable placement area.