DescriptionQ1000
Q1000FWMetaASIC interview problem
Saturating memory-error recorder
TechniquesSiliconReliabilitySystemVerilogSaturating counter
DifficultyMedium
TopicPost-Silicon Validation
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A silicon monitor reports corrected and uncorrectable memory events with an address. Implement saturating totals and a write-once record of the first uncorrectable address, including deterministic simultaneous-event and reset behavior.
Starting declarationSystemVerilog
input logic clk, rst_n, corrected, uncorrectable;
input logic [31:0] error_addr;
output logic [15:0] corrected_count, uncorrectable_count;
output logic first_uncorrectable_valid;
output logic [31:0] first_uncorrectable_addr;Example input and output
Use this case to check your interpretationInput
Before an edge: corrected_count=5, uncorrectable_count=2, valid=0; corrected=1, uncorrectable=1, error_addr=0x1000Output
After the edge: counts are 6 and 3, valid=1, first_uncorrectable_addr=0x1000Explanation
The event updates are independent, so both counts advance once, while the previously clear valid bit permits the first address capture.
02
Requirements (4)
- Increment each matching counter on its event and saturate independently at 16'hFFFF rather than wrapping.
- If corrected and uncorrectable are both 1 on one edge, increment both counters once.
- On the first uncorrectable event only, set the valid bit and capture error_addr; never overwrite the address until reset.
- Use synchronous active-low reset to clear both counters, the valid bit, and the stored first address.