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Part 3 · Timing and signoff

STA constraints, MMMC closure, ECOs, and release

Write the timing relationships precisely, scope constraints to functional intent, close coupled setup and hold failures across views, and release only when timing and physical evidence agree.

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15 of 15 practice questions shown.

  1. Q0212Separate skew, jitter, latency, and uncertaintyTiming & closure · EasySeparate clock latency, skew, jitter, and timing uncertainty.Free
  2. Q0580Compare static timing analysis with timing simulationTiming & closure · EasyCompare STA coverage with event-based timing simulation.Premium
  3. Q0595Calculate setup and hold slack with clock latencyTiming & closure · MediumCalculate setup and hold slack with explicit clock latency.Premium
  4. Q0114Classify timing-path startpoints and endpointsTiming & closure · EasyClassify valid timing-path startpoints and endpoints.Free
  5. Q1097Review and scope false-path candidatesTiming & closure · MediumProve a false-path candidate is functionally impossible.Premium
  6. Q0332Distinguish clock-group relationship typesTiming & closure · EasyDistinguish asynchronous, exclusive, and related clock groups.Premium
  7. Q0426Choose first-order setup and hold fixesTiming & closure · EasyChoose first-order setup and hold fixes without cross-check damage.Premium
  8. Q0644Find fmax for a half-cycle timing pathTiming & closure · MediumDerive Fmax for a half-cycle launch-to-capture path.Premium
  9. Q0715Use different setup and hold uncertaintyTiming & closure · MediumApply different setup and hold uncertainty budgets.Premium
  10. Q0816Explain CRPR in a timing reportTiming & closure · EasyExplain which shared clock pessimism CRPR removes.Premium
  11. Q1012Explain OCV derates and temperatureTiming & closure · MediumConnect OCV derates and temperature to early and late timing.Premium
  12. Q1025Pair setup and hold multicycle constraintsTiming & closure · MediumPair multicycle setup and hold constraints correctly.Premium
  13. Q0923Constrain a source-synchronous read strobeTiming & closure · MediumConstrain a source-synchronous read strobe and its data window.Premium
  14. Q0267Choose coupled setup and hold ECOsTiming & closure · HardSelect coupled setup/hold ECOs that survive every required view.Free
  15. Q0965Minimum cells for two-corner closureTiming & closure · HardFind the minimum cell changes that close two opposing corners.Premium

Timing contractsConstrain the sampled path, not the picture

Static timing compares data arrival against a required sampling window for every declared scenario. Clocks, exceptions, uncertainty, and variation define that window.

Concept model

Join launch, data, and capture on one ruler

  1. 0.0 nsLaunch edgeclock + tCQ
  2. 0.3 nsData startscell + wire delay
  3. 2.5 nsData arrivesarrival time
  4. 3.0 nsCapture edgerequired time
Setupslack = required − arrivalmax path · next capture edge
Holdslack = arrival − requiredmin path · same capture edge
Skew
capture − launch latency
Uncertainty
jitter + modeling margin
OCV
early/late path derates
CRPR
remove common-path pessimism
Setup
late dataMaximum-delay analysis asks whether data settles before the intended capture edge.
Hold
early dataMinimum-delay analysis asks whether old data remains stable after the active edge.
Skew
capture − launchPositive capture skew usually helps setup and hurts hold for the same edge relationship.
CRPR
shared clock pathCommon-path pessimism removal avoids charging incompatible variation twice on shared clock segments.

Setup protects the next capture boundary and hold protects the current one. Clock latency, skew, uncertainty, derates, and common-path pessimism change the two checks in different ways.

Strong answer

Setup checks a maximum-delay path against a later capture boundary, while hold checks a minimum-delay path against the current boundary. Speeding data helps setup but can hurt hold; delaying data helps hold but can consume setup margin.

Reason it through

  • Setup fixes include reducing logic depth, upsizing critical cells, buffering fanout, improving placement, or using safe clock skew.
  • Hold fixes usually add localized minimum delay or adjust clock arrival without changing the functional cycle relationship.
  • Every ECO needs multi-corner analysis because the setup-critical and hold-critical corners and paths can differ.
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Strong answer

Skew changes the relative launch and capture arrivals, uncertainty reserves margin for unmodeled clock variation, OCV derates model different path behavior, and CRPR removes impossible double counting on shared clock segments.

Reason it through

  • Positive capture skew generally adds setup time and removes hold margin for the same launch-capture relationship.
  • Setup and hold can use different uncertainty and derate values because their edge relationships and variation risks differ.
  • CRPR removes only pessimism associated with a physically common clock path; it does not erase real clock variation.
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Strong answer

An exception is valid only when it describes a real architectural sampling relationship: a false path is never functionally captured, a multicycle path is intentionally captured on a later edge, and clock groups declare defined clock relationships or their absence.

Reason it through

  • A setup multicycle usually needs a paired hold adjustment so the minimum-delay obligation remains on the intended edge.
  • Asynchronous clock groups remove cross-domain timing analysis only when a separate CDC structure and verification plan make that safe.
  • Exceptions should be narrow, reviewable, and matched to real startpoints, endpoints, and modes rather than broad naming patterns.
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Release evidenceClose every required scenario on one database

Tapeout readiness is an intersection, not a best result. Timing, signal integrity, power integrity, physical verification, and logical equivalence must all pass their required scope.

Concept model

Turn violations into bounded ECO loops

ModeCornerDominant checkState
FunctionalSS · low V · hotSetupreview
FunctionalFF · high V · coldHoldpass
Scan shiftSS · low V · hotIR / slewrepair
At-speed testFF · high V · coldCapture holdpass

Illustrative obligations only: dominant PVT and RC views depend on the libraries, test protocol, extracted design, and signoff methodology.

Setupsize · buffer · route · pipeline
Holddelay cell · route detour
SIspace · shield · resize
IR / EMstraps · vias · spread load
DRC / antennareroute · diode · layer hop
LVS / equivalenceconnectivity or netlist ECO
MMMC
all required viewsFunctional and test modes combine with voltage, process, temperature, and RC corners.
Physical
DRC + LVSGeometry must satisfy manufacturing rules and match the intended circuit connectivity.
Electrical
STA + SI + PITiming, coupling, voltage delivery, and current density use extracted implementation data.
Logical
equivalenceThe released implementation must remain functionally consistent with its reference design.

Classify the failing scenario, choose a root-cause fix, rerun the affected analyses, and then restore full signoff coverage. The released netlist and layout must remain logically and physically consistent.

Strong answer

MMMC closure means every required analysis view meets its acceptance criteria on the same releasable design, with modes, clocks, parasitics, libraries, voltage, process, temperature, derates, and exceptions configured consistently.

Reason it through

  • Functional, scan shift, at-speed test, and low-power modes can activate different clocks, paths, and constraints.
  • Maximum and minimum timing, SI, and power-integrity risks can peak in different process, voltage, temperature, and RC combinations.
  • Scenario reduction is safe only when dominance or equivalence is demonstrated and the reduced set remains documented.
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Strong answer

First confirm the violation and its model, then choose a localized root-cause fix, run fast incremental analysis, and finally reestablish full timing, physical, power, and equivalence signoff on the updated database.

Reason it through

  • Check clocks, exceptions, parasitics, noise, and scenario setup before modifying cells or routes.
  • Predict setup, hold, slew, capacitance, congestion, leakage, dynamic power, and cross-corner effects before selecting an ECO.
  • After implementation, rerun extraction and all affected analyses, then perform clean full-suite signoff rather than relying only on incremental reports.
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Strong answer

STA checks declared timing relationships, SI checks coupling effects, IR and EM check power delivery and conductor reliability, DRC checks geometry, LVS checks connectivity, and equivalence checks logical consistency with the reference.

Reason it through

  • The analyses are complementary: clean LVS does not prove timing, and clean STA does not prove manufacturable geometry or reliable power delivery.
  • A waiver needs a bounded rule, location, rationale, owner, and approval; it is not the same as a passing result.
  • All reports must reference the same final netlist, layout, extraction, constraints, libraries, and tool-qualified runset.
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