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Hardware interview practice

Separate ISA Guarantees from Core Implementation

MediumFirmwareC

An RTOS is being ported from an Armv8-A platform to an RV64 platform. Both implementations happen to have caches, an MMU, and out-of-order execution. Which statement is safe for the porting plan?

Choose one

Answer choices

  1. A. The instruction encodings, privilege architecture, exception details, page-table format, and memory-ordering rules must be ported to the target ISA; caches and out-of-order execution are implementation choices and do not make the two platforms binary- or barrier-compatible.
  2. B. RISC-V openness means every RV64 core has the same optional extensions and microarchitecture, while every Arm core is fixed by one company implementation.
  3. C. Because both cores have an MMU and caches, the same executable, page tables, and barrier instructions are guaranteed to work unchanged.
  4. D. Memory ordering is a compiler-only property, so device drivers need no ISA-specific fences or memory attributes on either platform.
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