Hardware interview practice
Quiesce before acknowledging power-down
A small accelerator may acknowledge a sleep request only after its last outstanding operation finishes. Write synthesizable SystemVerilog for the sleep handshake.
Starting point
Question code
input logic clk, rst_n;
input logic sleep_req, busy;
output logic sleep_ack, accept_work;Reviewed example
Work through one case
Input
sleep_req rises while busy=1, then sleep_req drops before busy clears.Expected output
accept_work goes low while draining, no sleep_ack is asserted, and the controller returns to awake.The request first blocks new work, but cancellation has priority in the draining state and prevents entry into asleep.
What to cover
Requirements
- In the awake state, accept_work=1 and sleep_ack=0; seeing sleep_req moves to a draining state and immediately makes accept_work=0.
- In draining, cancellation has priority: if sleep_req=0, return to awake without acknowledging; otherwise, if busy=0, enter asleep and assert sleep_ack=1.
- Remain asleep while sleep_req=1; when sleep_req becomes 0, return to awake on the next rising edge.
- Synchronous active-low reset enters awake; sleep_ack and accept_work must reflect the registered state with no latch.