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Hardware interview practice

Choose a low-power technique for a short idle interval

EasyLow PowerSystemVerilog

A compute block is idle for tens of cycles at a time. Its state must be preserved, it must resume in one cycle, and switching power is the dominant component. Which technique best matches these stated constraints?

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Answer choices

  1. A. Use glitch-free clock gating while idle so state is retained and clock-tree/sequential switching stops.
  2. B. Leave the clock running and add isolation only at the block outputs; isolation removes internal switching activity.
  3. C. Replace every cell with a low-threshold cell because that primarily reduces switching power without affecting leakage.
  4. D. Power-gate the block without retention on every idle interval, then reconstruct its lost state in one cycle.
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