Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Place isolation and retention correctly

Hardware interview practice

Place isolation and retention correctly

EasyLow PowerSystemVerilog

A switchable producer domain drives an always-on consumer. Some producer state must survive power-off, and producer outputs are invalid while its supply is off. Which low-power structures are required?

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Choose one

Answer choices

  1. A. Retention flops for the state that must survive, plus isolation on signals leaving the switchable domain before or while its supply turns off.
  2. B. Isolation alone, because clamping outputs automatically saves and restores all internal sequential state.
  3. C. Only clock gating, because stopping the clock removes leakage and preserves state through complete power removal.
  4. D. Retention flops alone, because retained internal state guarantees every powered-off output remains electrically valid.
Continue practicing

Related questions

Low PowerClassify CMOS power components→Low PowerChoose between an FPGA and a CPLD→Low PowerChoose a low-power technique for a short idle interval→
asic.fyi · Learn silicon end to end.info@asic.fyi