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Hardware interview practice

Overlapped versus non-overlapped implication in SVA

EasyTemporal ChecksSystemVerilog

If req is sampled at cycle N and ack must be high at N+1 or N+2, which property is correct?

Choose one

Answer choices

  1. A. req |-> ##[1:2] ack
  2. B. req |=> ##[1:2] ack
  3. C. req |-> ack[*2]
  4. D. req |=> ack[=0]
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