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Minimize a Three-Input Function with a Don't-Care

EasyRTL DesignSystemVerilog

For inputs ordered A,B,C with A as the most significant index bit, `F=1` at minterms 1,2,3,5,7 and input 0 is a don't-care. All other minterms are zero. Create the canonical form, minimize it with the don't-care, implement the result, and exhaustively check all care inputs.

Starting point

Question code

module logic_min(input logic A,B,C, output logic F);
// ones: m(1,2,3,5,7)
// don't-care: d(0)
// zeros: m(4,6)
// combinational implementation only
Reviewed example

Work through one case

Input
Case 1: A,B,C=0,1,0
Case 2: A,B,C=1,1,0
Case 3: A,B,C=0,0,0
Expected output
Case 1: Is minterm 2 -> F=1 from ~A.
Case 2: Is minterm 6 -> F=0 because ~A=0 and C=0.
Case 3: Is the don't-care -> the selected implementation outputs 1, which is permitted.

The shown result follows by applying this rule: The canonical minterm set and care/don't-care classification match the supplied table. The cases also demonstrate this requirement: Check all seven care inputs against the table; the chosen minimal implementation is allowed to output one at don't-care input 000.

What to cover

Requirements

  1. Write the canonical SOP for minterms 1,2,3,5,7 before simplification and mark minterm 0 as a don't-care rather than a required one or zero.
  2. Use the don't-care to form a four-cell group for `~A` and a four-cell group for `C`, yielding the minimal expression `F = ~A | C`.
  3. Implement the two-literal expression without latches and explain that B is absent because it does not affect any care result.
  4. Check all seven care inputs against the table; the chosen minimal implementation is allowed to output one at don't-care input 000.
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