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Identify Simulation Defaults for Variables and Nets

EasyDesign VerificationSystemVerilog

A four-state `logic q;` is never initialized, and a `wire w;` has no driver in a simulation. Which statement is correct before any assignment or driver is added?

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Answer choices

  1. A. The simulator may choose zero or one randomly for each value on every read.
  2. B. `q` is Z and `w` is X because variables float while nets store unknown data.
  3. C. Both values are guaranteed to be zero in simulation and in fabricated hardware.
  4. D. `q` reads as X and `w` resolves to Z in simulation; actual power-up state is technology- and implementation-dependent unless reset or initialization is guaranteed.
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