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Hardware interview practice

Build a reset-responsive nonblocking driver

HardUVM ComponentsSystemVerilog

Implement a clock-responsive ready/valid driver that uses try_next_item(), immediately idles during reset, waits one clean cycle after reset release, and retries an interrupted item.

Reviewed example

Work through one case

Input
item A is presented but reset asserts before handshake; reset releases; one full clean cycle passes; ready then accepts A
Expected output
pins idle throughout reset and release cycle; A is retried unchanged and item_done occurs once after acceptance

Reset aborts only the pin-level attempt, while the buffered sequence item remains owned for a post-reset retry.

What to cover

Requirements

  1. The main loop must keep observing reset even when no sequence is active.
  2. Reset aborts the pin-level attempt but preserves the buffered item for retry.
  3. Drive a known idle state throughout reset and for one complete release cycle.
  4. Complete the sequence item only after its post-reset handshake.
Continue practicing
UVM ComponentsCoordinate two sequencers with a virtual sequenceUVM ComponentsDrive a ready/valid interface correctlyUVM ComponentsDrive a multi-beat ready/valid transaction