Hardware interview practice
Combine Pre-Silicon Checks with FPGA Prototype Validation
An ASIC-oriented packet engine will also run on an FPGA prototype, where internal observation is limited and FPGA memories, clocks, and resets differ from the final ASIC implementation. Which verification strategy is strongest?
Choose one
Answer choices
- A. Probe every internal signal continuously on the FPGA, eliminating the need for assertions, scoreboards, trigger planning, or reproducible test seeds.
- B. Use lint, simulation, assertions, formal checks, scoreboards, and coverage before mapping; then run reproducible hardware traffic, clock/reset stress, and error cases with selected ILA probes, while treating FPGA-specific initialization, memories, clocks, and timing as prototype differences rather than ASIC signoff.
- C. Verify only the FPGA vendor wrappers because synthesizable user RTL behaves identically in every clock, reset, and unknown-state condition.
- D. Skip simulation once the RTL fits in the FPGA because passing long random traffic on hardware proves all internal corner cases and ASIC timing modes.